Infineon Technologies S25FLxS FL-S NOR Flash Memory Devices

Infineon Technologies S25FLxS FL-S NOR Flash Memory Devices are 2.7V to 3.6V or 1.65V to 3.6V V_IO Volt Non-volatile Memory. The S25FLxS FL-S NOR Flash Memory Devices use 65nm MIRRORBIT™ technology. Featuring the Eclipse™ architecture with a Page Programming Buffer, 256Mb S25FLxS FL-S NOR allows users to program up to 256-words. This results in more effective programming and erasing than prior generation SPI programs or erased algorithms. The devices connect to a host system via an SPI and support traditional SPI single bit serial input and output.

The S25FLxS FL-S NOR provides support for Double Data Rate read commands for SIO, DIO, and QIO. The S25FLxS FL-S NOR transfer address and read data on both edges of the clock. Using FL-S devices at the supported higher clock rates with QIO or DDR-QIO commands. The S25FLxS NOR instruction read transfer rate can match a traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. S25FLxS FL-S NOR offers high-density performance capabilities coupled with the flexibility and speed required by a variety of embedded applications. S25FLxS FL-S NOR memory devices are ideal for code shadowing, XIP, and data storage.

Features

CMOS 3.0Volt core with versatile I/O
Serial Peripheral Interface (SPI) with multi-I/O
- SPI clock polarity and phase modes 0 and 3
- Double Data Rate (DDR) option
- Extended addressing of 24- or 32-bit address options
- Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O command set and footprint compatible with S25FL-P SPI family
READ commands
- Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
- Common Flash Interface (CFI) data for configuration information
Programming (1.5Mbytes/s)
- 256 or 512Byte Page Programming buffer options
- Quad-Input Page Programming (QPP) for slow clock systems
- Automatic ECC -internal hardware Error Correction Code generation with single bit error correction
Erase (0.5 to 0.65Mbytes/s)
- Hybrid sector size option - physical set of thirty two 4-kbyte sectors at top or bottom of address space with all remaining sectors of 64kbytes, for compatibility with prior generation S25FL devices
- Uniform sector option - always erase 256-kbyte blocks for software compatibility with higher density and future devices.

Cycling Endurance
- 100,000 Program-Erase Cycles, minimum
Data Retention
- 20 Year Data Retention, minimum
Security features
- One Time Program (OTP) array of 1024 bytes
- Block Protection:
  - Status Register bits to control protection against program or erase of a contiguous range of sectors.
  - Hardware and software control options
- Advanced Sector Protection (ASP)
  - Individual sector protection controlled by boot code or password
Cypress® 65nm MIRRORBIT Technology with Eclipse™ Architecture
Core Supply Voltage of 2.7V to 3.6V
I/O Supply Voltage of 1.65V to 3.6V
- SO16 and FBGA packages
Temperature Range / Grade:
- Industrial (-40°C to +85°C)
- Industrial Plus (-40°C to +105°C)
- Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
- Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
- Automotive AEC-Q100 Grade 1 (-40°C to +125°C)
Packages (all Pb-free)
- 16-lead SOIC (300mil)
- WSON 6mm x 8mm
- BGA-24 6mm x 8mm
- 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options